Signals in digital circuits typically have one driver pin and one or more load pins. A logic transition on a signal during circuit operation commences at the driver of the signal and is received by each of the load pins at some point later in time. The propagation delay from a signal driver to each of its load pins depends on the routing topology, capacitance, and buffering in the signal path. For a multi-load signal, the propagation delay from the signal driver to each load may differ. This notion leads to an important signal property, called the signal “skew,” which is the difference in propagation delay of a signal routed to the different load pins. Similarly, “clock skew” refers to skew on the clock network. Clock skew has a considerable impact on the performance of sequential logic circuits, and can often reduce the performance of sequential circuits by reducing the permissible propagation time for combinational paths.